2.5v or 3.3v, 200-mhz, 1:18 clock distribution buffe r CY29942 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07284 rev. *c revised march 14, 2005 features ? 200-mhz clock support ? 2.5v or 3.3v operation ? lvcmos/lvttl clock input ? lvcmos-/lvttl-compatible inputs ? 18 clock outputs: drive up to 36 clock lines ? 110ps typical ou tput-to-output skew ? output enable control ? pin compatible with mpc942c ? available in industrial and commercial ? 32-pin lqfp package description the CY29942 is a low-voltage 200-mhz clock distribution buffer with an lvcmos or lvttl compatible input clock. all other control inputs are lvcmos/lvttl compatible. the eighteen outputs are 2.5v or 3.3v lvcmos or lvttl compatible and can drive 50 ? series or parallel terminated transmission lines. for series terminated transmission lines, each output can drive one or tw o traces giving the devices an effective fanout of 1:36. low output-to-output skews make the CY29942 an ideal clock distribution buffer for nested clock trees in the most demandi ng of synchronous systems. block diagram pin configuration tclk oe vdd 18 q0-q17 CY29942 q0 q1 q2 vdd q3 q4 q5 vss q17 q16 q15 vss q14 q13 q12 vdd q6 q7 q8 vdd q9 q10 q11 vss vss vss tclk nc oe nc vdd vdd 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25
CY29942 document #: 38-07284 rev. *c page 2 of 7 note: 1. pd = internal pull-down, pu = internal pull-up. pin description [1] pin name pwr i/o description 3tclk i, pd external reference/test clock input 5oe i, pu output enable . when high, all the outputs are enabled. when set low, the outputs are at high impedance. 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 q(17:0) vdd o clock outputs 7, 8, 16, 21, 29 vdd 3.3v or 2.5v power supply 1, 2, 12, 17, 25 vss common ground 4, 6 nc no connection
CY29942 document #: 38-07284 rev. *c page 3 of 7 maximum ratings [2] maximum input voltage relative to v ss : ............ v ss ? 0.3v maximum input voltage relative to v dd : ............. v dd + 0.3v storage temperature: ............. .............. ..... ?65c to + 150c operating temperature: ................................ ?40c to +85c maximum esd protection ............................................... 2 kv maximum power supply: ................................................5.5v maximum input current: ............................................20 ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). notes: 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 3. inputs have pull-up/pull-down resistors that effect input current. 4. driving series or parallel terminated 50 ? (or 50 ? to v dd /2) transmission lines. dc parameters: v dd = 3.3v 5% or 2.5v 5%, v ddc = 3.3v 5% or 2.5v 5%, over the specified temperature range. parameter description cond itions min. typ. max. unit v il input low voltage v ss 0.8 v v ih input high voltage 2.0 v dd v i il input low current [3] ?200 a i ih input high current [3] 200 a v ol output low voltage [4] i ol = 20 ma 0.5 v v oh output high voltage [4] i oh = ?20 ma, v ddc = 3.3v 2.4 v i oh = ?16 ma, v ddc = 2.5v 2.0 i ddq quiescent supply current 57ma i dd dynamic supply current v dd = 3.3v, outputs @ 150 mhz, cl = 15 pf 285 ma v dd = 3.3v, outputs @ 200 mhz, cl = 15 pf 335 v dd = 2.5v, outputs @ 150 mhz, cl = 15 pf 200 v dd = 2.5v, outputs @ 200 mhz, cl = 15 pf 240 z out output impedance v dd = 3.3v 8 12 16 ? v dd = 2.5v 10 15 20 c in input capacitance 4 pf
CY29942 document #: 38-07284 rev. *c page 4 of 7 notes: 5. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with loaded outputs. 6. outputs driving 50 ? transmission lines. 7. see figure 1 . 8. 50% input duty cycle. 9. across temperature and voltage ranges, includes output skew. 10. for a specific temperature and voltage, includes output skew. ac parameters [5] : v dd = 3.3v 5% or 2.5v 5%, v ddc = 3.3v 5% or 2.5v 5%, over the specified te mperature range parameter description conditions min. typ. max. unit fmax input frequency 200 mhz tpd ttl_clk to q delay [6, 7] v dd = 3.3v 1.8 3.3 3.8 ns v dd = 2.5v 2.3 3.8 4.4 foutdc output duty cycle [6, 7, 8] measured at v dd /2 45 55 % tskew output-to-output skew [6, 7] 110 200 ps tskew(pp) part-to-part skew [9] v dd = 3.3v 1.0 ns v dd = 2.5v 1.3 tskew(pp) part-to-part skew [10] 600 ps tr/tf output clocks rise/fall time [6, 7] 0.8v to 2.0v, v dd = 3.3v 0.2 1.1 ns 0.5v to 1.8v, v dd = 2.5v pulse generator z = 50 ohm zo = 50 ohm vtt zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm CY29942 dut figure 1. lvcmos_clk CY29942 test reference for v cc = 3.3v and v cc = 2.5v t pd lvcmos_clk q vcc gnd vcc /2 vcc gnd vcc /2 figure 2. lvcmos propagation delay (tpd) test reference vcc gnd vcc /2 t p t0 dc = tp / t0 x 100% figure 3. output duty cycle (foutdc)
CY29942 document #: 38-07284 rev. *c page 5 of 7 t sk(0) vcc gnd vcc /2 vcc gnd vcc /2 figure 4. output-to -output skew tsk(0) ordering information part number package type production flow CY29942ai 32 pin lqfp industrial,?40c to +85c CY29942ait 32 pin lqfp - tape and reel industrial, -?40c to +85c CY29942ac 32 pin lqfp commercial, 0c to +70c CY29942act 32 pin lqfp - tape and reel commercial, 0c to +70c lead-free CY29942axi 32 pin lqfp industrial, ?40c to +85c CY29942axit 32 pin lqfp - tape and reel industrial, ?0c to +85c CY29942axc 32 pin lqfp commercial, 0c to +70c CY29942axct 32 pin lqfp - tape and reel commercial, 0c to +70c
CY29942 document #: 38-07284 rev. *c page 6 of 7 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions all product and company names mentio ned in this document may be the tr ademarks of their respective holders. 32-lead thin plastic quad flatpack 7 x 7 x 1.4 mm a32.14 51-85088-*b
CY29942 document #: 38-07284 rev. *c page 7 of 7 document history page document title: CY29942 2.5v or 3.3v, 200-mhz, 1:18 clock distribution buffer document number: 38-07284 rev. ecn no. issue date orig. of change description of change ** 111095 02/07/02 brk new data sheet *a 116777 08/14/02 hwt added a commercial temp. range in the ordering information *b 122876 12/21/02 rbi add power up requirements to maximum rating information. *c 334117 see ecn rgl added lead-free devices added typical value for output-output skew
|
